IEEE

Cryogenic Plasma Etching Process Optimization Using a Wireless CryoTemp™ Metrology Wafer

Abstract: To enhance the etch profile fidelity in advanced 3D flash memory, a cryogenic plasma etching process is employed for the channel hole etch layer. Controlling wafer level temperature and ...
IEEE

High Rate and Selective Deep Reactive-Ion Etching Process for the Formation of High-Density Vertical Interconnects into Dielectric Build-Up Film

Abstract: In this work, DRIE is applied for the formation of vertical interconnects into the most mainstream dielectric build-up films. For the experiments, Evatec CLUSTERLINE® 600 tool is used that ...